1. Field of the Invention
The present invention generally relates to field isolation technology in silicon semiconductor devices and, more particularly, to techniques which use buried oxide (BOX) field isolation for commercial very large scale integrated (VLSI) circuits. The techniques according to the invention include use of the local oxidation of silicon (LOCOS) process to make the BOX isolation.
2. Description of the Prior Art
The purpose of a field oxide is to electrically isolate various active regions on a silicon chip. LOCOS is a steam process which is used to produce thermal silicon dioxide or SiO.sub.2 in the field region of a semiconductor device in a reasonable time. In a steam ambient, thermal oxide is selectively grown in field regions through patterned silicon nitride masks on the semiconductor surface. This process is effective because silicon nitride or Si.sub.3 N.sub.4 acts as a diffusion block to oxygen. A channel-stop implant, such as boron for n-channel devices, improves the isolation by further raising the field threshold voltage.
Field isolation created by a LOCOS process results in a so-called bird's beak region caused by lateral oxidation of the silicon substrate under the nitride mask. The nitride mask is stripped off after the oxidation. Because radiation hardening of the bird's beak in the LOCOS field oxide is a difficult task which is exacerbated by diffusion of the channel stop during LOCOS processing, workers in the field have been forced to seek alternative processing means.
As one alternative, BOX field isolation technology has been developed for application to VLSI devices. According to Kei Kurosawa, Tadashi Shibata and Hisakazu Iizuka in a paper entitled "A New Bird's-Beak Free Field Isolation Technology for VLSI Devices", presented at the International Electron Devices Meeting (IEDM) 1981, pages 384-387, BOX technology has improved dynamic memory cell density by 80% over that obtainable in devices made by LOCOS because the bird's beak is completely eliminated. T. Shibata, R. Nakayama, K. Kurosawa, S. Onga, M. Konaka and H. Iizuka in a paper entitled "A Simplified BOX (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories", presented at IEDM 9983, pages 27-30, state that BOX structures also have superior electrical characteristics.
The Kurosawa et al. paper describes a two-step oxide-burying process. According to that procedure, regions where active devices will be placed on a silicon substrate are defined by placement of aluminum patterns. The aluminum patterns act as hard masks which protect the active regions from the etching that is subsequently performed. The silicon substrate is first thermally oxidized, and aluminum masks are then placed on the oxide layer thus formed, to define active regions. The wafers are next etched in other than the masked, active regions by reactive ion etching (RIE). The resulting field regions in the silicon wafer are then implanted with boron, again using the aluminum patterns as masks. The trenches are thereafter filled with silicon dioxide by the two-step oxide-burying technique. The active region is thus defined by the aluminum mask and the final structure is free of bird's beak formation. The Kurosawa et al. paper also recognizes the undesirability of a channel leakage current occurring at the side walls of the trenches in the silicon substrate, and eliminates the parasitic channel formation by implanting boron in the walls.
The Shibata et al. paper describes a BOX process for metal oxide semiconductor field effect transistors (MOSFETs) with a simplified sequence of steps. SiO.sub.2 masks are used instead of aluminum, followed by taper etching of silicon using RIE to obtain silicon mesas. Boron is then implanted in the field region, and the silicon surfaces in the trench are thermally oxidized. The trench is next filled with chemical vapor deposited (CVD) silicon dioxide. Photoresist patterns are then placed to cover the silicon dioxide in the field areas, and a spin coating of photoresist is placed on top of the photoresist patterns to create a planar, double resist. RIE etchback with the two resist layers being sacrificed completes the process. While this BOX process constitutes a one-step channel filling process rather than a two-step process, the idea of filling trenches with SiO.sub.2 is the same in both instances. The Shibata et al. improvements lie in the elimination of aluminum masks and the use of taper etching for facilitating the trench filling process.
U.S. Pat. No. 4,333,965 to Chow et al. discloses another method of reducing lateral field oxidation in the vicinity of the active region. RIE is used in this method as well, but here a mesa is created by removing portions of the substrate and leaving a cap of silicon nitride, silicon dioxide, titanium, and photoresist material on top of the mesa. The substrate is next heated in an oxidizing atmosphere to convert the exposed surfaces in the field regions to silicon dioxide. The cap is then removed. The substrate is heated enough to cover the mesa and side walls with thermally produced SiO.sub.2. An etchback procedure is performed to expose the top of the mesa. The active region is defined by the top of the mesa and the field region is defined by the trenches created by etching.
The foregoing prior art procedures all suffer from the drawback of overetching during the etchback procedure. If the BOX process of Kurosawa et al. or Shibata et al. is used, for example, either the CVD deposited SiO.sub.2 or both the CVD deposited SiO.sub.2 and the thermally produced SiO.sub.2 may be overetched. A BOX structure where only the CVD deposited SiO.sub.2 is overetched leaves only a thin layer of thermal SiO.sub.2 to protect the top corner of the channel side wall against leakage current. Studies have shown that this portion of the side wall is very susceptible to experiencing radiation-induced threshold voltage shift. The electric field in the upper corner of a BOX structure where both the CVD deposited SiO.sub.2 and the thermal SiO.sub.2 are overetched is greatly enhanced. Thus, both structures experience side wall leakage current, the former after exposure to certain minimum levels of radiation, and the latter without exposure to any radiation at all.